● Led the verification of the NTPU module as part of the AONSS. ● Analyzed and understood the specifications, test plan and SOR document. ● Utilized RAL-based sequence to run tests, leveraging trace files provided by the IP team for module testing ● Identified and debugged test case failures, providing solutions and updates to the verification sequence to ensure alignment with requirements. ● Collaborated with cross-functional teams to resolve issues and ensure timely delivery of verification results.

1. 10 GB Ethernet MAC Verification with loop back mechanism (August’2023 - May’2024). The MAC layer controls how devices access the physical network medium (like Ethernet cables). It handles tasks such as addressing, frame assembly and disassembly, and controlling data flow. An Ethernet MAC with loopback mechanism operates in between data link layer and physical layer by using XGMII interface. The XGMII is functionally define an interface allowing independent development of MAC and PHY logic. The intention of providing this Loopback mode of operation is to permit a diagnostic or self-test function to perform the transmission and reception of a Protocol Data Unit, thus testing the transmit and receive data paths. Roles & Responsibilities: ● Understood specifications of MAC and XGMII of ETHERNET Protocol (IEEE 802.3). ● Extracted features of 10GB Ethernet MAC ● Developed and maintained Verification Plan Document to develop verification environment in UVM. ● Developed Testbench component Driver to provide stimulus to the transmitter part of MAC. ● Developed testplan and implemented testcases on bring up, undersized & oversized packet. 2. USB2.0 :Verification of USB host and device PHY (UTMI) models (August’2022 - June’2023). USB is a serial bus for connecting peripherals. It is controlled by host and there can be only one host per bus. The communication between host and device is in the form of USB Frames. Each USB frame consists of three packets Token packet, Data packet, Handshake packet. The intention of the project is verifying the features of PHY(UTMI) models of host and device and ensuring the successful communication between host and device of USB2.0. Roles & Responsibilities: ● Understood Protocol specifications of USB2.0. ● Extracted features. ● Developed start of frame packet, Token packet, data packet and Handshake packet to generate USB frame which is applied to transmit pins of host and device. ● Developed logic to calculate CRC5 and CRC16 in the base class. ● Developed Testplan and test cases. ● Debugged on testcase failures by analyzing log files and waveforms to find out root cause. 3. Design and Verification of Advanced Peripheral Bus (APB) Slave (December’2021 - June’2022). The APB is a part of the AMBA protocol family tailored for simple, low-bandwidth peripheral connections. Its non-pipelined protocol and low-cost design help achieve minimal power consumption and reduced interface complexity, making it ideal for certain types of peripheral interfaces. Roles & Responsibilities: ● Understood the protocol specifications. ● Developed design code for APB Slave in Verilog based on the state machine. ● Developed UVM TB environment which consists of an active agent (sequencer, driver and input monitor), passive agent (output monitor), scoreboard and coverage. ● Debugged in case of testcase failures.