← В ленту
Регистрация: 30.07.2025

Sri Ganga Pranav Godasi

Специализация: Design Verification Engineer
— I am aspiring Design Verification Engineer with hands-on experience in RTL functional verification using SystemVerilog and UVM. — During my internship at Vaaluka Solutions, I worked on verifying SoC modules including an Aligner, AXI Interconnect, and a 4-Port Switch, where I developed UVM-based testbenches, functional coverage models, and automated regression setups. — I have a strong understanding of RAL, assertions, randomization, and protocol compliance checks. — Passionate about verification methodologies, I continuously enhance my skills through advanced training courses.
Verilog centos C++ Windows Python
— I am aspiring Design Verification Engineer with hands-on experience in RTL functional verification using SystemVerilog and UVM. — During my internship at Vaaluka Solutions, I worked on verifying SoC modules including an Aligner, AXI Interconnect, and a 4-Port Switch, where I developed UVM-based testbenches, functional coverage models, and automated regression setups. — I have a strong understanding of RAL, assertions, randomization, and protocol compliance checks. — Passionate about verification methodologies, I continuously enhance my skills through advanced training courses.
Verilog centos C++ Windows Python

Портфолио

Verification of AXI DMA interconnect

● In this project, I focused on functional verification of an AXI interconnect system with multiple masters and slaves. ● I developed SystemVerilog/UVM-based verification components to validate DMA-driven data transfers, transaction routing, and protocol compliance. ● I implemented AXI read/write sequences to test concurrent master access scenarios, ensuring fairness in arbitration logic. ● Additionally, I performed waveform-level debugging to resolve issues in response handling and data integrity, contributing to a robust and reusable verification environment.

Verification of 4 port switch

● For the 4-Port Switch, I implemented a SystemVerilog verification environment designed to test single, multicast, and broadcast packet routing. ● I built reusable packet classes with constrained randomization, developed sequencer, driver, and monitor components, and set up parallel verification instances to stimulate all input ports. ● Using randomized traffic patterns and coverage metrics, I thoroughly verified switching accuracy and routing correctness, ensuring the design met functional requirements across diverse traffic conditions.

Verification of Aligner Module

● In the Aligner project, I was responsible for developing and executing the complete functional verification flow. ● I designed a UVM-based testbench that included sequencers, drivers, monitors, and a scoreboard to validate packet filtering and forwarding logic. ● I created constrained-random test sequences, functional coverage models, and assertions to ensure thorough feature verification, including CNT_DROP tracking, interrupt generation, and reset handling. ● I automated regression runs using Makefiles, managed version control with Git, and performed waveform-level debugging to identify and resolve packet alignment and FIFO handling issues. ● My contributions ensured comprehensive verification and improved test coverage for the module.

Скиллы

C/C++
UVM
Verilog HDL
SystemVerilog
Python 3
Vivado Design Suite
Questa Sim
UART
SPI
I2C
APB
AHB
AXI
Verible
Python
Windows
Linux CentOS

Опыт работы

Design Verification Engineer
с 02.2025 - По настоящий момент |Vaaluka Solutions
SystemVerilog, UVM, QuestaSim, Verible Lint Tool
● Underwent hands-on training in SystemVerilog and UVM, gaining expertise in RAL modeling, assertions, randomization techniques, and functional coverage concepts. ● Performed functional verification of multiple SoC modules, including Aligner, AXI Interconnect, and 4-Port Switch using SystemVerilog and UVM. ● Developed verification plans reviewed and validated by industry experts, built constrained-random testbenches, and designed coverage models to ensure comprehensive feature verification. ● Created and executed UVM sequences and regression setups with Makefile automation; managed codebase using Git and VerifTool. 1. Verification of Aligner Module: ● Designed a complete UVM-based verification environment for the Aligner module, including sequencer, driver, monitor, scoreboard, and functional coverage components. ● Developed constrained-random test sequences to validate packet filtering, CNT_DROP tracking, interrupt generation, and register behavior under multiple traffic scenarios. ● Created Makefile-driven regression automation with seeded randomization; debugged complex issues like packet alignment and FIFO push errors using waveform analysis. 2. Verification of AXI Interconnect: ● Implemented AXI read/write UVM sequences for validating DMA-based data transfers and ensuring correct transaction routing between masters and slaves. ● Verified arbitration and fairness logic by simulating concurrent master accesses to the same slave and ensuring priority handling and protocol compliance. ● Performed waveform-level debugging to analyze data integrity, response handling, and timing issues across interconnect channels. 3. Verification of 4-Port Switch: ● Developed a SystemVerilog-based verification testbench for a 4-port packet switch, supporting single, multicast, and broadcast packet routing. ● Created a reusable packet class with constrained randomization and enumeration-based typing to generate varied traffic scenarios. ● Built a layered verification setup with multiple parallel environments, validating correct packet routing under randomized multi-port traffic conditions.

Образование

Electronics and Communication Engineering (Бакалавр)
2021 - 2025
Vasavi College of Engineering

Языки

АнглийскийВыше среднего