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Регистрация: 30.07.2025

Faisal Saeed Awan

Специализация: Design Verification Engineer
— Design Verification Engineer with 2.5+ years in UVM-based verification of SoC IPs and high-speed interconnects. — Experienced in scalable testbenches, advanced sequences, coverage-driven verification flows, SystemVerilog, Assertions, AXI/APB, VIP integration, and achieving full coverage. — Strong in debugging, automation, and delivering first-pass silicon success.
Git Verilog Linux Функциональное тестирование Shell scripting Bitbucket Debugging
— Design Verification Engineer with 2.5+ years in UVM-based verification of SoC IPs and high-speed interconnects. — Experienced in scalable testbenches, advanced sequences, coverage-driven verification flows, SystemVerilog, Assertions, AXI/APB, VIP integration, and achieving full coverage. — Strong in debugging, automation, and delivering first-pass silicon success.
Git Verilog Linux Функциональное тестирование Shell scripting Bitbucket Debugging

Скиллы

Universal Verification Methodology
System Verilog
SoC verification
Debugging
Shell Scripting
Git
Bitbucket
SystemRDL 2.0
Functional Coverage
QuestaSim (Visualizer)
Synopsis VCS
IP Verification

Опыт работы

Design Engineer
с 10.2022 - По настоящий момент |CoMira Solutions
D2D Interconnect, SystemRDL, UVM, FIFO RTL, ALU
● Designed & implemented UVM testbench from scratch. ● Developed complex sequences for D2D link training & replay verification. ● Integrated & validated VIP-to-VIP protocol compliance for interconnects. ● Achieved 100% functional & code coverage, enabling first-pass silicon success. ● Created reusable AXI/APB verification environments, reducing dev time 30%. ● Verified FIFO with ALU integration via scoreboards & reference models.

Образование

Electronics (Магистр)
2020 - 2023
Ghulam Ishaq Khan Institute of Engineering Sciences and technology
Industrial Electronics Engineering (Бакалавр)
2011 - 2015
Institute of Industrial Electronics Engineering (IIEE)

Языки

УрдуРоднойАнглийскийСреднийХиндиПродвинутый