● As a core contributor to the verification team, made significant contributions to the validation of a 56GT/sx8 link (LLD) Low Latency Die-to-Die (D2D) interconnect using a UVM framework. Key contributions include: ● Verification Environment: Built a scalable UVM testbench from the ground up, featuring a SystemRDL- based register model for efficient DUT configuration and status monitoring. ● Advanced Sequence Development: Implemented complex verification scenarios to test the D2D logic. This involved creating dedicated sequences to verify the integrity of the link training process, ensuring a stable link was established, and validating the replay mechanism for guaranteed data acknowledgement during error conditions. ● VIP Integration: Executed a thorough VIP-to-VIP verification strategy to ensure seamless protocol compliance and interoperability between the connected dies. ● Coverage Closure: Drove the complete verification lifecycle, including rigorous debugging and analysis, to successfully attain all functional and code coverage objectives. ● Developed reusable UVM verification environments for AXI and APB protocols. ● Performed UVM based verification of a FIFO RTL design integrated with ALU. Developed scoreboards and reference model for comprehensive end-to-end validation.