● My role involves automatically generating SystemVerilog Assertions (SVAs) from natural language specifications and creating a UVM testbench. Additionally, it addresses low-data tasks, such as SystemVerilog Assertion generation, through a specialized solution called the ART Augmentation Environment. Automated RTL and Testbench (ART) - Sponsored by Siemens EDA: ● ART is an Electronic Design Automation (EDA) tool that was collaboratively developed during our third year in EECE2023. The aim of the tool is to transform the conventional approach to RTL design and verification. ● The Project aims to accelerate the generation of UVM testbenches and the creation of System Verilog Assertions from natural language specifications and from inline comments in the RTL and generating Sequence Items to trigger the assertions in addition to accelerating the design steps of finite state machines and top module connections. Acquired skills: ● Working with a state-of-the-art LLM. ● Developing a solution for the augmentation of low data tasks (Augmentation Environment). ● Developing Verilog parser. ● Developing algorithms to automate UVM complex environments generation. ● Developing complex and customized GUIs: circuits schematics and node editor. ● At the end of the project, we came out with an EDA tool supporting the following features: - Schematic (Block Diagram) Editor & Code Generator. - FSM Editor & Code Generator. - Basic Verilog Parser - UVM Configurator and Generator. - Text Classification model to classify Natural Language Assertions - Natural Language Assertions (NLA) to System Verilog Assertions translation (NLA to SVA). - Sequence Item Generation from System Verilog Assertions. - Building a solution for the augmentation of low data tasks. ● On top of that, we used PyQt to implement a user-friendly UI for all these features and integrated with customized QtScintilla Editor. Scientific Contribution: ● Presented paper at IEEE ICM 2024, this paper introduces ART UVM Generator, a python-based tool addressing the generation of UVM environments with three main features, Fast-Startup, Custom environment and Automated Hierarchical UVM.