Junior Verification Engineer

We are looking for a motivated Junior Verification Engineer to join our client's team. You will work on verifying complex digital designs, ensuring their functionality, performance, and reliability before tape-out. You will collaborate with design and verification teams to develop and execute test plans, debug failures, and contribute to improving verification methodologies.

This is an excellent opportunity for an early-career engineer to grow their expertise in UVM, System Verilog, and constrained-random verification while working on cutting-edge semiconductor projects.

Among responsibilities:

• Develop and execute verification test plans for digital IPs, subsystems, or SoCs.
• Implement and maintain UVM-based test benches using System Verilog.
• Create and optimize constrained-random test sequences to achieve coverage goals.
• Debug RTL and testbench failures, working closely with design engineers.
• Write assertions (SVA) and functional coverage models to ensure thorough verification.
• Automate regression testing and analyze coverage metrics.
• Contribute to verification methodology improvements.
• Collaborate with cross-functional teams in a fully remote environment.

Requirements:

• 0-2 years of experience in digital verification (academic/internship/project experience acceptable).
• Familiarity with SystemVerilog and UVM (or OVM/VMM).
• Basic understanding of constrained-random verification and coverage-driven methodologies.
• Knowledge of scripting for automation.
• Experience with simulation tools.

Work format:

USA PST, 9-18 5/2 remote